Intel announces new FPGA families

Image source: Intel PSG

Intel has announced these new/future FPGA families:

Intel® Agilex™ D-Series

For midrange FPGA applications like studio cameras, 8K video transport, and wireless infrastructure.

This new family incorporates an upgraded hard processor system (HPS), Enhanced DSP with AI Tensor Block, MIPI I/O support, and a hardened time-sensitive network controller (TSN). Intel Agilex D-Series devices also keep features from previous families like the 2nd-generation Intel® Hyperflex™ FPGA Architecture and high-speed SerDes transceivers.

Future Intel® Agilex™ FPGAs (codenamed Sundance Mesa)

Under design, for a variety of applications, including workloads in industrial, broadcast, automotive, communications, consumer, test and measurement, and medical markets.

The new Intel Agilex device family inherits many of the most important architectural features of earlier Intel Agilex devices including the second-generation Intel® Hyperflex™ FPGA Architecture, which places Hyper-Registers throughout the FPGA.

These devices combine the Intel Agilex FPGA fabric with a broad set of intellectual property (IP) and connectivity options including high-speed transceivers that support data rates to 28.1 Gbps and the PCIe 4.0 interface protocol.

The new Intel Agilex device family also supports DDR4, LPDDR4, DDR5, and LPDDR5 SDRAM; general purpose I/O with output voltages ranging from 1.05 V to 3.3 V; in addition a hard processor system (HPS) based on a multi-core Arm Cortex CPU with two Arm Cortex-A76 processor cores that can run as fast as 1.8 GHz and two Arm Cortex-A55 processor cores that can run as fast as 1.5 GHz.

Intel® Agilex™ FPGAs with R-Tile

These devices include the Compute Express Link (CXL) intellectual property (IP) to the Intel Quartus Prime Software IP library. This CXL hard + soft IP builds upon the existing PCI Express (PCIe) 5.0 capabilities of the Intel® Agilex™ I-Series and M-Series FPGAs and SoCs that incorporate “R” transceiver tiles. The initial release of this IP supports CXL v1.1. A planned future IP release will provide a software-only upgrade path for these Intel Agilex FPGAs and SoCs by adding support for CXL v2.0.

CXL devices will be used in diverse areas such as high-performance computing (HPC), artificial intelligence (AI), machine learning (ML), data analytics, and other specialized tasks.

Direct RF FPGAs Intel® Direct RF FPGAs can perform direct analog RF signal conversion for multiple analog input and output channels in a variety of topologies supporting up to 16 channels and various configurations with channel rates as fast as 64 Gsps.

The new devices in this portfolio of Intel Direct RF FPGA devices now extend the I/O capabilities of Intel Agilex and Intel Stratix 10 FPGAs to the analog domain using ADC and DAC chiplets that have been co-developed with partners and then composed into packaged devices using Intel’s EMIB and AIB technologies.

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