from Hacker News https://ift.tt/2F4pxmH
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find another way [1] to implement this. * Passing a zeroed structure is fragile, * but at least we do not pass garbage. * * [1] One way would be that ndo_neigh_setup() never touch * struct neigh_parms, but propagate the new neigh_setup() * back to ___neigh_create() / neigh_parms_alloc() |
22 days ago | drivers/net/bonding/bond_main.c |
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Handle KVM_MR_MOVE |
1 month ago | arch/powerpc/kvm/book3s_hv.c |
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* bypass the initialize in sriov for now |
1 month ago | drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c |
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* bypass the initialize in sriov for now |
1 month ago | drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c |
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* bypass the terminate in sriov for now |
1 month ago | drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c |
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* bypass the terminate in sriov for now |
1 month ago | drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c |
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* bypass the initialize in sriov for now |
1 month ago | drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c |
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* bypass the terminate in sriov for now |
1 month ago | drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c |
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The INTB interrupt is used for both PTP TX timestamp interrupt * and preemption status change interrupt on each port. * * - Get txtstamp if have * - handle preemption. Without handling it, driver may get * interrupt storm. |
1 month ago | drivers/net/dsa/ocelot/felix.c |
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It needs to continue working on debugging with semaphore for GFXHUB as well. |
1 month ago | drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c |
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It needs to continue working on debugging with semaphore for GFXHUB as well. |
1 month ago | drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c |
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It needs to continue working on debugging with semaphore for GFXHUB as well. |
1 month ago | drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c |
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It needs to continue working on debugging with semaphore for GFXHUB as well. |
1 month ago | drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c |
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It needs to continue working on debugging with semaphore for GFXHUB as well. |
1 month ago | drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c |
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It needs to continue working on debugging with semaphore for GFXHUB as well. |
1 month ago | drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c |
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It needs to continue working on debugging with semaphore for GFXHUB as well. |
1 month ago | drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c |
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It needs to continue working on debugging with semaphore for GFXHUB as well. |
1 month ago | drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c |
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remove this once fw does it |
1 month ago | drivers/net/wireless/intel/iwlwifi/pcie/rx.c |
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* currently we don't set the antenna but letting the NIC * to decide which antenna to use. This should come from BIOS. |
1 month ago | drivers/net/wireless/intel/iwlwifi/mvm/fw.c |
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* NOTE about '.balign 4': * * To make atomic update of patched instruction available we need to guarantee * that this instruction doesn't cross L1 cache line boundary. * * As of today we simply align instruction which can be patched by 4 byte using * ".balign 4" directive. In that case patched instruction is aligned with one * 16-bit NOP_S if this is required. * However 'align by 4' directive is much stricter than it actually required. * It's enough that our 32-bit instruction don't cross L1 cache line boundary / * L1 I$ fetch block boundary which can be achieved by using * ".bundle_align_mode" assembler directive. That will save us from adding * useless NOP_S padding in most of the cases. * * switch to ".bundle_align_mode" directive using whin it will be * supported by ARC toolchain. |
1 month ago | arch/arc/include/asm/jump_label.h |
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log? return different code? |
1 month ago | drivers/fsi/fsi-master-aspeed.c |
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confirm that 0x70 was okay |
1 month ago | drivers/fsi/fsi-master-aspeed.c |
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determine an appropriate value |
1 month ago | drivers/fsi/fsi-master-aspeed.c |
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We could avoid skb_cow_data() if skb has no frag_list * e.g. by skb_fill_page_desc() to add another page to the skb * with the wanted tailen... However, page skbs look not often, * so take it easy now! * Cloned skbs e.g. from link_xmit() seems no choice though :( |
1 month ago | net/tipc/crypto.c |
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handle p_memsz != p_filesz |
1 month ago | sound/soc/codecs/rt5677.c |
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* Rotating/reflecting YUV buffers is not supported at this time. * Only RGB[AX] variants are supported. |
1 month ago | drivers/gpu/drm/mediatek/mtk_disp_ovl.c |
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* If we use READ_ONCE / WRITE_ONCE for j_commit_request we can * get rid of pointless j_state_lock traffic like this. |
1 month ago | fs/jbd2/transaction.c |
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* dummy implement for pcie_replay_count sysfs interface * |
1 month ago | drivers/gpu/drm/amd/amdgpu/nv.c |
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ideally DSA ports would have a single dp->link_dp member, * and no dst->rtable nor this struct dsa_link would be needed, * but this would require some more complex tree walking, * so keep it stupid at the moment and list them all. |
1 month ago | include/net/dsa.h |
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* SNB,IVB,HSW can while VLV,CHV may hard hang on looping batchbuffer * if GEN6_PM_UP_EI_EXPIRED is masked. * * verify if this can be reproduced on VLV,CHV. |
2 months ago | drivers/gpu/drm/i915/gt/intel_rps.c |
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* this bit should only be enabled when really needed, then * disabled when not needed anymore in order to save power. |
2 months ago | drivers/gpu/drm/i915/intel_pm.c |
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Abort the process here. |
2 months ago | drivers/staging/media/sunxi/cedrus/cedrus_h265.c |
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VE_DEC_H265_DEC_PPS_CTRL1_FLAG_TILES_ENABLED |
2 months ago | drivers/staging/media/sunxi/cedrus/cedrus_h265.c |
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* Reset XGMI Pstate back to default * revise this when xgmi dpm is functional |
2 months ago | drivers/gpu/drm/amd/powerplay/arcturus_ppt.c |
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* Force XGMI Pstate to highest or lowest * revise this when xgmi dpm is functional |
2 months ago | drivers/gpu/drm/amd/powerplay/arcturus_ppt.c |
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convert to AQ time |
2 months ago | drivers/net/ethernet/aquantia/atlantic/aq_ptp.c |
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* ZONE_DEVICE support requires to identify * memmaps that were actually initialized. |
2 months ago | fs/proc/page.c |
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* ZONE_DEVICE support requires to identify * memmaps that were actually initialized. |
2 months ago | fs/proc/page.c |
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* ZONE_DEVICE support requires to identify * memmaps that were actually initialized. |
2 months ago | fs/proc/page.c |
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* FXOS8700 - NXP IMU (accelerometer plus magnetometer) * * IIO core driver for FXOS8700, with support for I2C/SPI busses * * Buffer, trigger, and IRQ support |
2 months ago | drivers/iio/imu/fxos8700_core.c |
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* adux1020.c - Support for Analog Devices ADUX1020 photometric sensor * * Copyright (C) 2019 Linaro Ltd. * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> * * Triggered buffer support |
2 months ago | drivers/iio/light/adux1020.c |
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* This function is called from dpu debugfs and as part of atomic * check. When called from debugfs, the crtc->mutex must be held to * read crtc->state. However reading crtc->state from atomic check isn't * allowed (unless you have a good reason, a big comment, and a deep * understanding of how the atomic/modeset locks work (<- and this is * probably not possible)). So we'll keep the WARN_ON here for now, but * really we need to figure out a better way to track our operating mode |
2 months ago | drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c |
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for renoir |
2 months ago | drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c |
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Fix this function to calcualte correct values. There are known issues with this function currently that will need to be investigated. Use hardcoded known good values for now. struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool); struct clk_limit_table *clk_table = &bw_params->clk_table; int i; dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator; dcn2_1_ip.max_num_dpp = pool->base.pipe_count; dcn2_1_soc.num_chans = bw_params->num_channels; for (i = 0; i < clk_table->num_entries; i++) { dcn2_1_soc.clock_limits[i].state = i; dcn2_1_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; dcn2_1_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; dcn2_1_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz; dcn2_1_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 16 / 1000; } dcn2_1_soc.clock_limits[i] = dcn2_1_soc.clock_limits[i - i]; dcn2_1_soc.num_states = i; |
2 months ago | drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c |
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* Ideally we really want a GPU reset here to make sure errors * aren't propagated. Since I cannot find a stable way to reset the GPU * at this point it is left as a . |
2 months ago | drivers/gpu/drm/i915/i915_sysfs.c |
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need to implement a proper lane mapping for Renoir. |
2 months ago | drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c |
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* enable clock gating * * It is not written in DP enabling sequence but "PHY Clockgating * programming" states that clock gating should be enabled after the * link training but doing so causes all the following trainings to fail * so not enabling it for now. |
3 months ago | drivers/gpu/drm/i915/display/intel_ddi.c |
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skip this for smb2/smb3 |
3 months ago | fs/cifs/inode.c |
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* this can be optimized for huge pages: if a series of pages is * physically contiguous and part of the same compound page, then a * single operation to the head page should suffice. |
3 months ago | mm/gup.c |
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fix dc bugs and remove this split threshold thing |
3 months ago | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c |
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ue will trigger an interrupt. * * When “Full RAS” is enabled, the per-IP interrupt sources should * be disabled and the driver should only look for the aggregated * interrupt via sync flood |
3 months ago | drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c |
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* (brendanhiggins@google.com): replace the arrays that keep track of the * order of allocation and freeing with strict mocks using the IN_SEQUENCE macro * to assert allocation and freeing order when the feature becomes available. |
3 months ago | lib/kunit/test-test.c |
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* (brendanhiggins@google.com): We should probably have some type of * variable timeout here. The only question is what that timeout value * should be. * * The intention has always been, at some point, to be able to label * tests with some type of size bucket (unit/small, integration/medium, * large/system/end-to-end, etc), where each size bucket would get a * default timeout value kind of like what Bazel does: * https://ift.tt/37lsQ4U * There is still some debate to be had on exactly how we do this. (For * one, we probably want to have some sort of test runner level * timeout.) * * For more background on this topic, see: * https://ift.tt/2F0NmM6 |
3 months ago | lib/kunit/try-catch.c |
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* If sysctl_hung_task is active, just set the timeout to some * value less than that. * * In regards to the above if we decide on variable * timeouts, this logic will likely need to change. |
3 months ago | lib/kunit/try-catch.c |
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* * kunit_test_suite() - used to register a &struct kunit_suite with KUnit. * * @suite: a statically allocated &struct kunit_suite. * * Registers @suite with the test framework. See &struct kunit_suite for * more information. * * NOTE: Currently KUnit tests are all run as late_initcalls; this means * that they cannot test anything where tests must run at a different init * phase. One significant restriction resulting from this is that KUnit * cannot reliably test anything that is initialize in the late_init phase; * another is that KUnit is useless to test things that need to be run in * an earlier init phase. * * (brendanhiggins@google.com): Don't run all KUnit tests as * late_initcalls. I have some future work planned to dispatch all KUnit * tests from the same place, and at the very least to do so after * everything else is definitely initialized. |
3 months ago | include/kunit/test.h |
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Always make new connection for now (?) |
3 months ago | fs/cifs/sess.c |
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check if changed channel, band |
3 months ago | drivers/staging/wfx/sta.c |
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Distill probe resp; remove TIM and any other beacon-specific * IEs |
3 months ago | drivers/staging/wfx/sta.c |
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#define MULTICAST_FILTERING 0 |
3 months ago | drivers/staging/wfx/sta.c |
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BSS_CHANGED_QOS |
3 months ago | drivers/staging/wfx/sta.c |
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add DBDC support |
3 months ago | drivers/net/wireless/mediatek/mt76/mt7615/mac.c |
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* Actions Semi Owl SoCs SD/MMC driver * * Copyright (c) 2014 Actions Semi Inc. * Copyright (c) 2019 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> * * SDIO support |
3 months ago | drivers/mmc/host/owl-mmc.c |
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ipv6 support |
3 months ago | fs/cifs/cifsroot.c |
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The function will only serve to keep the pointers to the "oper" and "admin" * schedules valid in relation to their base times, so when calling dump() the * users looks at the right schedules. * When using full offload, the admin configuration is promoted to oper at the * base_time in the PHC time domain. But because the system time is not * necessarily in sync with that, we can't just trigger a hrtimer to call * switch_schedules at the right hardware time. * At the moment we call this by hand right away from taprio, but in the future * it will be useful to create a mechanism for drivers to notify taprio of the * offload state (PENDING, ACTIVE, INACTIVE) so it can be visible in dump(). * This is left as . |
3 months ago | net/sched/sch_taprio.c |
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Need input parameter to tell current DCHUB pipe tie to which OTG * VTG is within DCHUBBUB which is commond block share by each pipe HUBP. * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG |
3 months ago | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c |
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:for CNVC set scale and bias registers if necessary |
3 months ago | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c |
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Other registers are not yet used |
3 months ago | drivers/gpu/drm/i915/intel_uncore.c |
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* This will update the table sum with new records. * * What happens when the EEPROM table is to be wrapped around * and old records from start will get overridden. |
3 months ago | drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c |
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* Extend multiple boot memory regions support in the kernel * for this platform. |
3 months ago | arch/powerpc/platforms/pseries/rtas-fadump.h |
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Add upper time limit for the delay |
3 months ago | arch/powerpc/platforms/pseries/rtas-fadump.c |
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Add upper time limit for the delay |
3 months ago | arch/powerpc/platforms/pseries/rtas-fadump.c |
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Add upper time limit for the delay |
3 months ago | arch/powerpc/platforms/pseries/rtas-fadump.c |
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* Handle frame_num wraparound as described in section * '8.2.4.1 Decoding process for picture numbers' of the spec. * This logic will have to be adjusted when we start * supporting interlaced content. |
3 months ago | drivers/staging/media/hantro/hantro_h264.c |
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* Validated limit is 4k, but has 5k should * work apart from the following features: * - Ytile (already limited to 4k) * - FP16 (already limited to 4k) * - render compression (already limited to 4k) * - KVMR sprite and cursor (don't care) * - horizontal panning ( verify this) * - pipe and plane scaling ( verify this) |
3 months ago | drivers/gpu/drm/i915/display/intel_display.c |
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evaluate how to lower or disable all dcn clocks in screen off case |
3 months ago | drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c |
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* Reenabling clock gating seems to break subsequent SMU operation * on the I2C bus. My guess is that SMU doesn't disable clock gating like * we do here before working with the bus. So for now just don't restore * it but later work with SMU to see if they have this issue and can * update their code appropriately |
3 months ago | drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c |
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Eventually add something to printk so we can format the rad * like this: 1.2.3 |
3 months ago | drivers/gpu/drm/drm_dp_mst_topology.c |
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To reduce the number of credit update messages, * don't update credits as long as lots of space is available. * Note: the limit chosen here is arbitrary. Setting the limit * too high causes extra messages. Too low causes transmitter * stalls. As stalls are in theory more expensive than extra * messages, we set the limit to a high value. experiment * with different values. |
3 months ago | net/vmw_vsock/virtio_transport_common.c |
| 4 months ago | drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | |
| 4 months ago | drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | |
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Implement support for gen-12 CCS modifiers |
4 months ago | drivers/gpu/drm/i915/display/intel_sprite.c |
| 4 months ago | drivers/usb/cdns3/ep0.c | |
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* Last condition latch INIT signals on vCPU when * vCPU is in guest-mode and vmcb12 defines intercept on INIT. * To properly emulate the INIT intercept, SVM should implement * kvm_x86_ops->check_nested_events() and call nested_svm_vmexit() * there if an INIT signal is pending. |
4 months ago | arch/x86/kvm/svm.c |
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add support for other clients... |
4 months ago | drivers/soc/qcom/ocmem.c |
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gpu uses phys_to_offset, but others do not.. |
4 months ago | drivers/soc/qcom/ocmem.c |
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* add more once ocmem_allocate() is clever enough to * deal with multiple clients. |
4 months ago | include/soc/qcom/ocmem.h |
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add support for other clients... |
4 months ago | drivers/soc/qcom/ocmem.c |
| 4 months ago | drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c | |
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oswin to think about what to do for cursor |
4 months ago | drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c |
| 4 months ago | drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c | |
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take the max between luma, chroma chunk size? |
4 months ago | drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c |
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check if ppe apply for both luma and chroma in 422 case |
4 months ago | drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c |
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ip_param |
4 months ago | drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c |
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check if ppe apply for both luma and chroma in 422 case |
4 months ago | drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c |
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take the max between luma, chroma chunk size? |
4 months ago | drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c |
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oswin to think about what to do for cursor |
4 months ago | drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c |
| 4 months ago | drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c | |
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check if ppe apply for both luma and chroma in 422 case |
4 months ago | drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c |
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take the max between luma, chroma chunk size? * okay for now, as we are setting chunk_bytes to 8kb anyways |
4 months ago | drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c |
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oswin to think about what to do for cursor |
4 months ago | drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c |
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